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PEDL7048-01-01
1 Semiconductor ML7048-01
3-Channel Single Rail CODEC
This version:
Oct. 2001
Preliminary
GENERAL DESCRIPTION
The ML7048 is a three-channel single rail CMOS CODEC LSI. This device contains filters for A-to-D and D-toA conversions of voice signals ranging 300 to 3400 Hz. The ML7048 is designed for a single power supply and low power applications and contains three-channel A-toD and D-to-A converters on a single chip, and achieves a reduced footprint and external component parts. The ML7048 is best suited for ISDN terminal and digital telephone terminal applications.
FEATURES
* Single 5 V Power Supply Operation * Using - ADC and DAC Technique * Low Power Consumption 3-Channel Operating Mode: typical: 140 mW max.:174 mW Power Saving Mode: (PDN = "1", PDN1 to 3 = "0") typical: 15 mW max.: 26 mW Power Down Mode: (PDN = "0") typical: 0.05 mW max.: 0.3 mW * ITU-T Companding Law: -law * PCM Interface: 3-Channel Independent or 3-Channel Continuous Serial Interface Pin Selectable * Master Clock: 12.288 MHz or 15.360 MHz Pin Selectable * Transmission Clocks: 64, 128, 256, 512, 1024, 2048 kHz 96, 192, 384, 768, 1536 kHz * Adjustable Transmit Gain for Each Channel * Built-in Reference Voltage Supply * Differential Analog Output can Directly Drive a 600 Transformer. * Package: 44-pin Plastic QFP (QFP44-P-910-0.80-2K) (Product name: ML7048-01GA)
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BLOCK DIAGRAM
Compressor Compressor
AIN1- AIN1+ GSX1 AIN2- AIN2+ GSX2 AIN3- AIN3+ GSX3
RC LPF
- AD CONV.
BPF
RC LPF
- AD CONV.
TCONT
DOUT1 DOUT2 DOUT3 XSYNC
BPF
RC LPF
- AD CONV.
BPF
Compressor
BCLK Expander RC LPF - DA CONV. LPF P/S
AOUT1+
AOUT1- Expander RCONT
RSYNC DIN1 DIN2 DIN3
AOUT2+
RC LPF
- DA CONV.
LPF
AOUT2- Expander
AOUT3+
RC LPF
- DA CONV.
LPF
AOUT3- Power Cont. & DLL & Clock Gen. MCKSEL MCK PDN PDN1 PDN2 PDN3
SGC VDDA VDD AG DG SG Gen.
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PIN CONFIGURATION (TOP VIEW)
42 AOUT1+
41 AOUT1-
44 AIN1-
37 PDN3
36 PDN2
35 PDN1
43 GSX1
AIN1+ 1 VDDA 2 AOUT2- 3 AOUT2+ 4 GSX2 5 AIN2- 6 AG 7 AIN2+ 8 VDDA 9 SGC 10 AIN3+ 11 AIN3- 12 GSX3 13 AOUT3+ 14 AOUT3- 15 AG 16 DG 17 VDD 18 MCKSEL 19 MCK 20 BCLK 21 P/S 22
34 PDN 33 TEST3 32 DOUT3 31 DOUT2 30 DOUT1 29 DG 28 DIN3 27 DIN2 26 DIN1 25 RSYNC 24 XSYNC 23 TEST2
44-Pin Plastic QFP
39 DG 38 VDD
40 AG
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PIN DESCRIPTION
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Symbol AIN1+ VDDA AOUT2- AOUT2+ GSX2 AIN2- AG AIN2+ VDDA SGC AIN3+ AIN3- GSX3 AOUT3+ AOUT3- AG DG VDD MCKSEL MCK BCLK P/S TEST2 XSYNC RSYNC DIN1 DIN2 DIN3 DG DOUT1 DOUT2 DOUT3 TEST3 PDN PDN1 PDN2 PDN3 VDD DG AG AOUT1- AOUT1+ GSX1 AIN1- Type I -- O O O I -- I -- O I I O O O -- -- -- I I I I I I I I I I -- O O O I I I I I -- -- -- O O O I Description Channel-1 Transmit Amp Non-inverting Input Analog Power Supply Channel-2 Receive Amp Inverting Output Channel-2 Receive Amp Non-inverting Output Channel-2 Transmit Amp Output Channel-2 Transmit Amp Inverting Input Analog Ground Channel-2 Transmit Amp Non-inverting Input Analog Power Supply Analog Signal Ground Channel-3 Transmit Amp Non-inverting Input Channel-3 Transmit Amp Inverting Input Channel-3 Transmit Amp Output Channel-3 Receive Amp Non-inverting Output Channel-3 Receive Amp Inverting Output Analog Ground Digital Ground Digital Power Supply Master Clock Frequency Select Signal Master Clock PCM Signal Shift Clock 3-Channel Independent/3-Channel Continuous Serial Interface Select Signal Test Control Signal 2 Transmit Sync Signal Receive Sync Signal Channel-1 PCM Signal Input Channel-2 PCM Signal Input Channel-3 PCM Signal Input Digital Ground Channel-1 PCM Signal Output Channel-2 PCM Signal Output Channel-3 PCM Signal Output Test Control Signal 3 Power Down Control Signal Channel-1 Power Down Control Signal Channel-2 Power Down Control Signal Channel-3 Power Down Control Signal Digital Power Supply Digital Ground Analog Ground Channel-1 Receive Amp Inverting Output Channel-1 Receive Amp Non-inverting Output Channel-1 Transmit Amp Output Channel-1 Transmit Amp Inverting Input
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PIN FUNCTIONAL DESCRIPTION
AIN1+, AIN2+, AIN3+, AIN1-, AIN2-, AIN3-, QSX1, GSX2, GSX3 AIN1+, AIN1- and GSX1 are the transmit inputs and transmit level adjustment pins for Channel 1, AIN2+, AIN2- and GSX2 are those for Channel 2. AIN3+, and AIN3- and GSX3 are those for Channel 3. AIN1+, AIN2+ and AIN3+ are non-inverting inputs for the op-amp. AIN1-, AIN2- and AIN3- are inverting inputs for the op-amp. GSX1, GX2 and GX3 are the outputs for op-amp. Do the level adjustment as described below. If AINn- and AINn+ are not used, connect AINn- to GSXn and AINn+ to SGC. During power saving and power down modes, GSX1, GSX2, and GSX3 outputs are at a high impedance. During power down mode in each channel, the GSX output of a channel in power down mode is at a high impedance.
GSXn Channel n analog input R2n C1n R1n AINn- AINn+ Channel n gain Gain = R2n/R1n 10 R1: Variable R2 > 20 k C1n > 1/(2 x 3.14 x 30 x R1n) R1 + R2 < 500 k
SGC
SG Gen.
AOUT1+, AOUT1-, AOUT2+, AOUT2-, AOUT3+, AOUT3- AOUT1+ and AOUT1- are the receive analog output pins for Channel 1, AOUT2+ and AOUT2- are those for Channel 2, and AOUT3+ and AOUT3- are those for Channel 3. AOUT1- is the inverting output for AOUT1+, AOUT2- is for AOUT2+, and AOUT3- is for AOUT3+. A load of 600 or more can be driven between AOUT1+ and AOUT1-, AOUT2+ and AOUT2-, and AOUT3+ and AOUT3-. The output signal has an amplitude of 3.4 Vpp above and below the signal ground voltage (SG) when the digital signal of 3.17 dBm0 is input to DIN1, DIN2, and DIN3. During power saving and power down modes, the AOUT1+, AOUT1-, AOUT2+, AOUT2-, AOUT3+, and AOUT3- outputs are at a high impedance. During power down mode in each channel, the AOUTn+ and AOUTn- of a channel in power down are at a high impedance. SGC Bypass capacitor pin used to generate the signal ground voltage level. Connect a 1 F capacitor with excellent high frequency characteristics between the SGC pin and the AG pin. MCK Master clock input pin. The frequency is 12.288 MHz or 15.360 MHz. The frequency is switched by MCKSEL. This master clock may be asynchronous with BCLK, RSYNC, and XSYNC. MCKSEL Master clock frequency select signal input pin. Input a 12.288 MHz clock to the MCK pin when MCKSEL is "0". Input a 15.360 MHz clock to the MCK pin when MCKSEL is "1". PDN Power down control signal input pin. When PDN is "0", all circuits are in power down mode.
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PDN1, PDN2, PDN3 PDN1 is the power down control signal input pin for Channel 1, PDN2 is for Channel 2, and PDN3 is for Channel 3. When PDN is "1" and PDN1, PDN2, and PDN3 are "0s", the corresponding channel goes in power saving mode (all analog circuits except the reference voltage generation circuit are being powered down). P/S Signal input pin for selecting either 3-channel independent serial interface or 3-channel continuous serial interface. When P/S is "0", 3-channel independent serial interface, in which the input/output of each channel is made through DIN1 to 3 and DOUT1 to 3 independently, is selected. When P/S is "1", 3-channel continuous serial interface, in which the input/output of each channel is made from DIN1 and DOUT1 continuously. When 3-channel continuous serial interface is selected, DOUT2 and DOUT3 pins are at a high impedance. Connect the DIN2 and DIN3 pins to the digital ground (DG). BCLK PCM signal shift clock input pin for DIN1, DIN2, DIN3, DOUT1, DOUT2, and DOUT3. The frequency is equal to the data rate. The clock frequencies available are 64, 96, 128, 192, 256, 384, 512, 1024, 1536, and 2048 kHz. When P/S is "1" and 3-channel continuous serial interface is selected, the frequencies of 64, 96, and 128 kHz cannot be used. RSYNC Receive synchronizing signal input pin. This signal selects necessary 8-bit PCM data from serial PCM signals for the DIN1, DIN2 and DIN3 pins. This synchronizing signal must be synchronized in phase with BCLK (generated from BCLK). XSYNC Transmit synchronizing signal input pin. This synchronizing signal must be synchronized in phase with BCLK (generated from BCLK). The DPLL circuit is synchronized in phase with XSYNC. DIN1, DIN2, DIN3 When P/S is "0" and 3-channel independent serial interface is selected, DIN1 is the PCM signal input pin for Channel 1, DIN2 is for Channel 2, and DIN3 is for Channel 3. When P/S is "1" and 3-channel continuous serial interface is selected, DIN1 is the PCM signal input pin for each channel and data is input in the order of Channel 1, Channel 2 and Channel 3. At that time, connect DIN2 and DIN3 to the digital ground (DG). The PCM signal data rate is equal to the frequency of BCLK. The PCM signal is shifted at the falling edge of BCLK. The MSD of PCM data is identified at the rising edge of RSYNC.
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DOUT1, DOUT2, DOUT3 When P/S is "0" and 3-channel independent serial interface is selected, DOUT1 is the PCM signal output pin for Channel 1, DOUT2 is for Channel 2, and DOUT3 is for Channel 3. When P/S is "1" and 3-channel continuous serial interface is selected, DOUT1 is the PCM signal output pin for each channel and data is output in the order of Channel 1, Channel 2, and Channel 3. At that time, DOUT2 and DOUT3 are at a high impedance state. The PCM signal is sequentially output starting from MSD in synchronization with the rise of BCLK. (MSD may be output at the rising edge of XSYNC depending on the timing of BCLK and XSYNC.) These pins are at a high impedance during the time other than PCM data output bits. These pins also are at a high impedance during power down mode and power saving mode. These pins must be internally connected to pull-up resistors because the output form is of open-drain. For coding law, the ITU-T Recommend -law is employed.
PCMIN / PCMOUT -law Input/output level M S D 1 1 0 0 D 2 0 1 1 0 D 3 0 1 1 0 D 4 0 1 1 0 D 5 0 1 1 0 D 6 0 1 1 0 D 7 0 1 1 0 D 8 0 1 1 0
+ full scale +0 -0 - full scale
Table 1 Coding law VDDA +5V power supply for analog signal circuits. Use an analog power supply system of equipment used. Connect a bypass capacitor of 1 F with excellent high frequency characteristics and a capacitor of 10 F between this pin and the AG pin. AG Ground pin for analog signal circuits. VDD +5V power supply pin for digital signal circuits. Although this pin and VDDA are not connected internally, these pins must be connected on the printed circuit board. DG Ground pin for digital signal circuits. Although this pin and AG are not connected internally, these pins must be connected on the printed circuit board. TEST2, TEST3 These pins are used for device test. These device test pins must be connected to the DG pin.
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PDN 0 1 1
PDNn 0/1 0 1
DOUTn H 11111111 Converted output
Table 2 Power Control vs. DOUT Output Status
PDN
PDN1
PDN2
PDN3
GSX1, AOUT1 High impedance High impedance Operating Depending on PDN1 Depending on PDN1
GSX2, AOUT2 High impedance High impedance Depending on PDN2 Operating Depending on PDN2
GSX3, AOUT3 High impedance High impedance Depending on PDN3 Depending on PDN3 Operating
SGC Connected to AG with a resistor of about 50 k Operating Operating Operating Operating
0 1 1 1 1
0/1 0 1 0/1 0/1
0/1 0 0/1 1 0/1
0/1 0 0/1 0/1 1
Table 3 Power Control vs. Analog Output Status
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ABSOLUTE MAXIMUM RATINGS
Parameter Power Supply Voltage Analog Input Voltage Digital Input Voltage Storage Temperature Symbol VDD VAIN VDIN TSTG Condition -- -- -- -- Rating -0.3 to +7.0 -0.3 to VDD+0.3 -0.3 to VDD+0.3 -55 to +150 Unit V V V C
RECOMMENDED OPERATING CONDITIONS
Parameter Power Supply Voltage Operating Temperature Analog Input Voltage High Level Input Voltage Low Level Input Voltage MCK Frequency Symbol VDD TOP VAIN VIH VIL FMCK Condition Voltage must be fixed -- Gain = 1 All Digital Input Pins MCKSEL = "0" MCKSEL = "1" BCLK XSYNC, RSYNC MCK, BCLK All Digital Input Pins BCLK to XSYNC XSYNC to BCLK BCLK to RSYNC RSYNC to BCLK XSYNC, RSYNC DIN1 to 3 DIN1 to 3 Pull-up Resistor, DOUT1 to 3 DOUT1 to 3 XSYNC, RSYNC Between SGC and AG Min. 4.75 -30 -- 2.2 0 -100ppm -100ppm Typ. 5.0 -- -- -- -- 12.288 15.360 Max. 5.25 +85 2.26 VDD 0.8 +100ppm +100ppm Unit V C VPP V V MHz
BCLK Frequency Sync Pulse Frequency Clock Duty Ratio Digital Input Rise Time Digital Input Fall Time Transmit Sync Pulse Setting Time Receive Sync Pulse Setting Time Sync Pulse Width DIN Set-up Time DIN Hold Time Digital Output Load Allowable Jitter Width Bypass Capacitor for SGC
FBCLK FSYNC DCLK TIR TIF TXS TSX TRS TSR TWS TDS TDH RDL CDL TJT CSG
64k, 128k, 256k, 512k, 1.024M, 2.048M 96k, 192k, 284k, 768k, 1.536M -- 40 -- -- 50 50 50 50 1 BCLK 50 50 0.5 -- -- 1 8 50 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 60 50 50 -- -- -- -- 100 -- -- -- 50 500 --
Hz kHz % ns ns ns ns ns ns s ns ns k pF ns F
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ELECTRICAL CHARACTERISTICS
DC and Digital Interface Characteristics
(VDD = 4.75 to 5.25 V, Ta = -30 to +85C) Parameter Symbol IDD1 Power Supply Current IDD2 IDD3 High Level Input Leakage Current Low Level Input Leakage Current Digital Output Low Voltage Digital Output Leakage Current Input Capacitance IIH IIL VOL IO CIN Condition 3CH Operating Mode, No Signal PDN = "1", PDN1 = PDN2 = PDN3 = "1" Power Saving Mode, PDN = "1", PDN1 = PDN2 = PDN3 = "0" Power Down Mode, PDN = "0" All inputs fixed All Digital Input Pins VI = VDD All Digital Input Pins VI = 0 V DOUT1 to 3, Pull-up = 0.5 k DOUT1 to 3, High Impedance State -- Min. -- -- -- -- -- 0 -- -- Typ. 28.0 3.0 0.01 -- -- 0.2 -- 5 Max. 33.0 5.0 0.05 10 10 0.4 10 -- Unit mA mA mA A A V A pF
Analog Interface Characteristics
(VDD = 4.75 to 5.25 V, Ta = -30 to +85C) Parameter SGC Rise Time Symbol TSGC Condition SGC to AG 0.1 F Rise time to 90% of max. level Min. -- Typ. -- Max. 100 Unit ms
Transmit Analog Interface Characteristics
(VDD = 4.75 to 5.25 V, Ta = -30 to +85C) Parameter Input Resistance Output Load Resistance Output Load Capacitance Output Amplitude Offset Voltage Symbol RINX RLGX CLGX VOGX VOSGX Condition AIN1, AIN2 GSX1, GSX2 with respect to SG voltage *1 Gain = 1 Min. 10 20 -- -1.13 -50 Typ. -- -- -- -- -- Max. -- -- 30 +1.13 +50 Unit M k pF V mV
*1 -2.73 dBm (600) = 3.17 dBm0 (-law) = 2.26 VPP
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Receive Analog Interface Characteristics
(VDD = 4.75 to 5.25 V, Ta = -30 to +85C) Parameter Output Load Resistance Output Load Capacitance Output Amplitude Offset Voltage Symbol RLAO CLAO VOAO VOSAO Condition AOUT1, AOUT2 AOUT3 with respect to inverting output AOUT1, AOUT2, AOUT3 AOUT1, AOUT2, AOUT3, RLAO=0.6 k with respect to inverting output AOUT1, AOUT2, AOUT3 with respect to SG voltage Min. 0.6 -- -1.7 -100 Typ. -- -- -- -- Max. -- 50 +1.7 +100 Unit k pF V mV
AC Characteristics
(VDD = 4.75 to 5.25 V, Ta = -30 to +85C) Parameter Symbol Loss T1 Loss T2 Loss T3 Loss T4 Loss T5 Loss T6 Loss R1 Loss R2 Loss R3 Loss R4 Loss R5 SDT1 SDT2 SDT3 SDT4 SDT5 SDR1 SDR2 SDR3 SDR4 SDR5 GTT1 GTT2 GTT3 GTT4 GTT5 GTR1 GTR2 GTR3 GTR4 GTR5 NIDLET NIDLER Freq. 60 300 1020 3000 3300 3400 100 1020 3000 3300 3400 Condition Level Min. 25 -0.15 0 (Attenuation) -0.15 -0.15 0 -0.15 -0.15 -0.15 0 36 36 36 30 25 36 36 36 30 25 -0.2 -0.2 -0.6 -1.2 -0.2 DIN to AOUTn -0.2 -0.6 -1.2 -- -- Typ. 45 +0.15 Reference +0.02 +0.1 0.6 +0.04 Reference +0.07 +0.20 0.6 43 41 39 34 31 43 41 39 34 31 +0.02 Reference +0.06 +0.3 +0.5 0 Reference -0.02 -0.1 -0.2 -76 -88 Max. -- +0.20 +0.20 +0.80 0.80 +0.2 +0.20 +0.80 0.8 -- -- -- -- -- -- -- -- -- -- +0.2 +0.2 +0.6 +1.2 +0.2 +0.2 +0.6 +1.2 -72 -82 dB Unit
Transmit Frequency Response
Receive Frequency Response
0
(Attenuation)
dB
Transmit Signal to Distortion Ratio
1020
Receive Signal to Distortion Ratio
1020
Transmit Gain Tracking
1020
Receive Gain Tracking
1020
Idle Channel Noise
-- --
3 0 -30 -40 -45 3 0 -30 -40 -45 3 -10 -40 -50 -55 3 -10 -40 -50 -55 -- --
*2
dB
*2
dB
dB
dB
AINn = SG *2 DIN = 0 code *2
dBrn0p
*2 P-message Filter is used
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AC Characteristics (Continued)
(VDD = 4.75 to 5.25 V, Ta = -30 to +85C) Parameter Symbol AVT AVR 1020 AVTT AVRT TD TGD T1 TGD T2 Transmit Group Delay TGD T3 TGD T4 TGD T5 TGD R1 TGD R2 Receive Group Delay TGD R3 TGD R4 TGD R5 Cross Talk Attenuation Discrimination Out of Band Spurious Signal Frequency Distortion Intermoduration Distortion CRT CRR CRCH DIS OBS SFDT SFDR IMDT IMDR PSRT1 Power Supply Noise Rejection Ratio PSRT2 PSRR1 PSRR2 Digital Output Delay Time DOUT Signal Output Delay Time AOUT Signal Output TSD TXD1 TXD2 TDDO TDAO 4.6 to 72k 300 to 3.4k 1020 fa = 470 fb = 320 0 to 4k 4 to 50k 0 to 4k 4 to 50k DOUTn Pull-up resister = 0.5 k CL = 50 pF and 1 LSTTL Signal rise time after power on by PDNn *5 Signal rise time after power on by PDNn *5 100 mVrms *4 0 0 0 -4 1020 0 1020 500 600 1000 2600 2800 500 600 1000 2600 2800 Trans to Receive Receive to Trans Channel to Channel 0 to 4 kHz 4.6 kHz to 1000 kHz 0 to 4 kHz 2 fa - fb 0 *3 0 *3 0 0 Condition Freq. Level VDD = 5 V, Ta = 25C VDD = 5 V, Ta = 25C VDD = 4.75 to 5.25 V Ta = -40 to 85C A to A Mode BCLK = 2048 kHz Min. 0.535 0.806 -0.3 -0.3 -- -- -- -- -- -- -- -- -- -- -- 80 75 80 30 -- -- -- -- -- 40 50 40 50 20 20 20 -- -- Typ. 0.555 0.835 -- -- 0.54 0.26 0.16 0.02 0.05 0.07 0.00 0.00 0.00 0.06 0.09 85 80 85 32 -37.5 -50 -48 -52 -52 44 55 45 56 -- -- -- 4 4 Max. 0.574 Vrms 0.864 0.3 0.3 0.6 0.75 0.35 0.125 0.125 0.75 0.75 0.35 0.125 0.125 0.75 -- -- -- -- -35 -40 -40 -40 -40 -- -- -- -- 100 100 100 -- -- ms ms ns dB dB dB dBm0 dBm0 dB ms ms dB Unit
Absolute Level (Initial Difference) Absolute level (Deviation of Temperature and power) Absolute Delay
ms
*3 Minimum value of the group delay distortion *4 The measurement under idle channel noise *5 The rise time of SGC by PDN is not included. DOUT and AOUT will not rise before inputting XSYNC.
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TIMING DIAGRAM
BCLK XSYNC DOUTn TXS TXD1
1 TSX
2 TWS TSD MSD
3
4
5
6
7
8
D2
D3
TXD2 D4
D5
D6
D7
D8
Note: In the above diagram, 3-channel independent serial interface is selected. When 3-channel continuous serial interface is selected, 24-bit data is output from DOUT1 in the order of Channel 1, Channel 2, and Channel 3. Figure 1 Transmit side Timing Diagram
BCLK RSYNC DINn TRS
1 TSR
2 TWS
3
4
5
6
7
8
TDS D3
TDH D4 D5 D6 D7 D8
MSD
D2
Note: In the above diagram, 3-channel independent serial interface is selected. When 3-channel continuous serial interface is selected, 24-bit data is input to DIN1 in the order of Channel 1, Channel 2, and Channel 3. Figure 2 Receive Side Timing Diagram
PDN SGC TSGC PDNn DOUTn TDDO High Impedance AOUTn TDAO SG Level
Note: DOUT and AOUT will not rise before inputting XSYNC. Figure 3 SGC, DOUT, AOUT Outputs Timing
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APPLICATION CIRCUITS
When 3-channel independent serial interface is selected
+5 V ML7048-01 GSX1 Channel 1 analog input 20 k 1 F 20 k AIN1- AIN1+ GSX2 Channel 2 analog input 20 k 1 F 20 k AIN2- AIN2+ GSX3 Channel 3 analog input 20 k 1 F 20 k AIN3- AIN3+ MCK Channel 1 analog output Channel 1 analog inverting output Channel 2 analog output Channel 2 analog inverting output Channel 3 analog output Channel 3 analog inverting output AOUT1+ AOUT1- BCLK XSYNC RSYNC AOUT2+ AOUT2- PDN PDN1 AOUT3+ AOUT3- PDN2 PDN3 Power Down Control Channel 1 Power Down Control Channel 2 Power Down Control Channel 3 Power Down Control DIN1 DIN2 DIN3 DOUT1 DOUT2 DOUT3 Channel 1 PCM Signal Output Channel 2 PCM Signal Output Channel 3 PCM Signal Output Channel 1 PCM Signal Input Channel 2 PCM Signal Input Channel 3 PCM Signal Input Master clock Input Bit Clock Input Sync Signal Input
SGC 1 F +5 V 10 F 0V 1 F AG DG VDDA VDD MCKSEL P/S TEST2 TEST3 * When MCK is 15.360 MHz, connect MCKSEL to VDD.
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When 3-channel continuous serial interface is selected
+5 V ML7048-01 GSX1 Channel 1 analog input 20 k 1 F 20 k AIN1- AIN1+ GSX2 Channel 2 analog input 20 k 1 F 20 k AIN2- AIN2+ GSX3 Channel 3 analog input 20 k 1 F 20 k AIN3- AIN3+ MCK Channel 1 analog output Channel 1 analog inverting output Channel 2 analog output Channel 2 analog inverting output Channel 3 analog output Channel 3 analog inverting output AOUT1+ AOUT1- BCLK XSYNC RSYNC AOUT2+ AOUT2- PDN PDN1 AOUT3+ AOUT3- PDN2 PDN3 Power Down Control Channel 1 Power Down Control Channel 2 Power Down Control Channel 3 Power Down Control Master clock Input Bit Clock Input Sync Signal Input DIN1 DIN2 DIN3 PCM Signal Input DOUT1 DOUT2 DOUT3 PCM signal Output
SGC 1 F +5 V 10 F 0V 1 F AG DG VDDA VDD MCKSEL P/S TEST2 TEST3 * When MCK is 15.360 MHz, connect MCKSEL to VDD.
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APPLICATION NOTE
Pull-up Resistor for the DOUT Pin Use an optimal value of pull-up resistor for the DOUT pin considering the frequency and load capacitance of BCLK used. If a small value of pull-up resistor is used, the distortion characteristics may be degraded and current consumption also may be increased. Select a pull-up resistance referencing the following calculation conditions. Calculation conditions: If SYNC and BCLK have risen and data is looped between DOUT and DIN, data can be normally input and output.
R PULL
1 - 20ns 4 x FBCLK = ( ) CL
XSYNC, RSYNC
FBCLK : Frequency of BCLK CL : Load capacitance of DOUTn 20ns : Internal delay
BCLK t = RPULL x CL DOUTn
Calculation example:
BCLK (Hz) 64k 128k 256k 512k 1.024M 2.048M RPULL (k) CL = 10 pF 388.6 193.3 95.7 46.8 22.4 10.2 CL = 20 pF 194.3 96.7 47.8 23.4 11.2 5.1 CL = 50 pF 77.7 38.7 19.1 9.4 4.5 2.0 CL = 100 pF 38.9 19.3 9.7 4.7 2.2 1.0
Selection of resistance value: If the calculated resistance is more than 100 k, use a 100 k resistor. Since the calculated resistance +10% is allowable, you can use a typical resistance a little higher than the calculated resistance.
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Cross-talk between Channels This device contains a 3-channel CODEC. The circuits and layout of this device have been designed so that the internal cross-talk between channels is to be as small as possible. The pins also are carefully placed. It is required to design your printed circuit board considering the following descriptions. Transmit Side: AN1+, AN1-, AIN2+, AIN2-, AIN3+, and AIN3- are the input pins for op-amps with a high resistance. Consequently, if the wiring patterns of these pins are close to the wiring patterns of other signals, cross-talk may be caused. And a longer wiring pattern generates noises. The wiring pattern must be as short as possible and must not be close to the patterns of other signals. In addition, connect a ground pattern between these wiring patterns and the wiring patterns of other signals. AIN1+, AIN2+, and AIN3+ are connected to SGC. Connect a bypass capacitor to the SGC pin as closely as possible and place a wiring pattern for AIN+, AIN2+, and AIN3+ separately. Receive Side: AOUT1+, AOUT1-, AOUT2+, AOUT2-, AOUT3+, and AOUT3- are the outputs for op-amps with a low resistance. Although the cross-talk caused by wiring patterns is small when compared with the transmit side, Avoid placing the wiring patterns of these pins closely to the wiring patterns of other signals. RSYNC Timing Data that is input from DINn is latched at the rising edge of BCLK corresponding to the trailing edge of the last bit. If the latch timing and the internal processing timing (25.390 s from the rise of XSYNC) are overlapped, data slip (data is deleted or the same data is output twice) data error may occur. Set the timing so that the latch timing and internal processing timing are not within 500 ns considering the jitter of DPLL.
XSYNC RSYNC BCLK DINn 25.390 s Last bit Latch timing Internal processing timing
Relationship between MCK and BCLK, XSYNC, RSYNC Although MCK may be asynchronous with BCLK, XSYNC, and RSYNC, take note of the following. If MCK and BCLK, XSYNC, RSYNC are generated from the different oscillation sources (ex. two crystal oscillators are used) with the same frequency, the difference in frequency may cause a beat. If this beat frequency is within the band, the characteristics may be degraded.
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1 Semiconductor
ML7048-01
RECOMMENDATIONS FOR ACTUAL DESIGN
* To assure specified electrical characteristics, use bypass capacitors with excellent high frequency characteristics for the power supply and keep them as close as possible to the device pins. * Connect the AG pin and DG pin each other as closely as possible. Connect to the system ground with low impedance. * Connect the VDDA pin to the VDD pin as closely as possible and connect them to the analog power supply at a low impedance. * Directly mount this device onto the printed circuit board without using an IC socket. Unless unavoidable, use short lead type socket. * When mounted on a frame, use electromagnetic shielding, if any electromagnetic emission sources such as power supply transformers surround the device. * Keep the voltage on the VDD pin not lower than -0.3 V even instantaneously to avoid latch-up phenomenon when turning the power on. * Use a low noise power supply (having low level high frequency spike noise or pulse noise) to avoid erroneous operation and the degradation of the characteristics of these device.
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PEDL7048-01-01
1 Semiconductor
ML7048-01
PACKAGE DIMENSIONS
(Unit: mm)
QFP44-P-910-0.80-2K
Mirror finish
5
Notes for Mounting the Surface Mount Type Package
Package material Lead frame material Pin treatment Package weight (g) Rev. No./Last Revised
Epoxy resin 42 alloy Solder plating (5m) 0.41 TYP. 4/Nov. 28, 1996
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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PEDL7048-01-01
1 Semiconductor
ML7048-01
NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2001 Oki Electric Industry Co., Ltd.
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